1. Field of the Invention
The present invention relates to a circuit board structure with capacitors embedded therein and a method for fabricating the same and, more particularly, to a circuit board structure with capacitors embedded therein and a method for fabricating the same, which can improve the flexibility of circuit layout.
2. Description of Related Art
Currently, the relentless progress in semiconductor fabricating process and electronic functions of microelectronic devices has lead to a highly integrated development of semiconductor chips. Quantity of input/output terminals and density of wiring in package structures increase as semiconductor chips develop toward high integration. However, as the density of wiring in a package structure increases, the noise also increases. Generally, in order to obviate noise or compensate electricity, passive components, e.g. resistors, capacitors, and inductors, are installed in a semiconductor chip package structure to eliminate noise and to stabilize circuits to thereby meet the requirements of microelectronic devices.
In conventional methods, utilizing surface mount technology (SMT) integrates most passive components onto a surface of a packaging substrate, such that the flexibility of wiring layout on the surface is restricted, and the occupied space is unfavorable to shrinkage of package size.
In view of the aforementioned drawbacks, many studies relative to lamination methods have appeared in recent years. High dielectric coefficient material is laminated between two copper layers and then electrode plates and circuits are formed to fabricate capacitors. FIG. 1 shows a perspective view of a packaging substrate structure laminated with capacitors, wherein the process thereof comprises: providing a core substrate 10 having an inner circuit layer 11 having an inner electrode plate 111; and forming a high dielectric material layer 12 on the inner circuit layer 11, and forming an outer circuit layer 13 having a plurality of conductive pads 132 and an outer electrode plate 131 on the high dielectric material layer 12 to thereby make a capacitor 17 through the outer electrode plate 131, the inner electrode plate 111, and a part of the high dielectric material layer 12 therebetween. The inner circuit layer 11 and the outer circuit layer 13 as well as the circuits on two sides of the substrate are electro-connected by plated through holes (PTH) 14. In addition, a solder mask 15 is formed on the surfaces of the above structure, wherein the solder mask 15 has a plurality of openings 151 to expose the conductive pads 132 thereby accomplishing the packaging substrate.
However, the prior art forms a whole piece of high dielectric material layer within a packaging substrate, wherein the used part of the high dielectric material layer for a capacitor is merely the one between the inner electrode plate and the outer electrode plate, while the unused part of the high dielectric material layer electrically contacts with the circuits, such that the structure has several drawbacks: first, the unused part of the high dielectric material layer causes waste, unfavorable to reducing the cost; second, owing to the poor fluidity of the high dielectric material, voids and poor uniformity of thickness occur; third, the unused part of the high dielectric material layer contacts the circuits, so that parasitic capacitance occurs to interfere with electrical qualities; finally, because the electrode plates and the circuits are laid together in a circuit layer, the flexibility of layouts of both the electrode plates and the circuits is compromised.
In addition, another conventional process has been developed. As shown in FIG. 2A, a metal layer 21 is provided; a high dielectric material layer 22 and another metal layer 23 are formed on part of the metal layer 21; and then a dielectric layer 24 is formed on the metal layer 21 to accomplish a carrier 2 with capacitors embedded therein. Subsequently, as shown in FIG. 2B, a core board 2′ comprising a dielectric layer 25 and circuit layers 26 on two surfaces of the dielectric layer 25 is provided; the core board 2′ is laminated between two carriers 2; the carriers 2 are drilled and the metal layer 21 is patterned to form a circuit layer 271 and conductive vias 272 so as to obtain a circuit board structure with capacitors embedded therein, as shown in FIG. 2C. In comparison to the prior art shown in FIG. 1, the prior art shown in FIGS. 2A to 2C does not use a whole piece of high dielectric material layer and thereby can avoid the drawbacks: the unused part of the high dielectric material layer causes waste, unfavorable to reducing the cost; the manufacture for capacitors of high quality is difficult; and parasitic capacitance occurs to interfere with electrical qualities. However, in the structure, the electrode plates and the circuits are still laid together in a circuit layer, such that the flexibility of layouts of both the electrode plates and the circuits is compromised, and parallel connection between the capacitors to provide more capacitance cannot be achieved.
Therefore, it is desirable to provide an improved circuit board structure with capacitors embedded therein and fabricating method thereof to mitigate and/or obviate the aforementioned drawbacks.